The present invention relates to a ferroelectric memory device, and more particularly relates to measures taken to improve the reliability thereof.
Over the past few years, portable communications terminals, IC cards and the like have been rapidly popularized around the world. To operate these types of electronic units more efficiently, nonvolatile semiconductor memory devices for use in these units are increasingly required to operate at an even lower voltage and at an even higher speed while consuming even lower power. A ferroelectric memory device is one of strong candidate nonvolatile memory devices that are expected to fulfill these requirements at the same time. A device of this type includes a ferroelectric capacitor, in which a ferroelectric film is sandwiched between a pair of electrodes. Data can be stored thereon in a nonvolatile manner depending on whether the ferroelectric material within the capacitor is polarized in one direction or the other, which is reversed by the application of a positive or negative electric field. In rewriting data stored on a ferroelectric memory device, such an electric field as reversing the direction of polarization in the ferroelectric film has only to be applied. Accordingly, the ferroelectric memory device can advantageously contribute to higher-speed operation with lower voltage applied and lower power dissipated.
FIG. 4 is a plan view of an array of memory cells in a conventional ferroelectric memory device as viewed from above its layer in which bit lines are formed. FIG. 5 is a vertical cross-sectional view of part of the array taken along the line V—V in FIG. 4.
As shown in FIG. 5, an active region OD is formed to be surrounded by a LOCOS film 52 on an Si substrate 51. Within this active region OD, source/drain doped layers 53, and polysilicon gates 54 are formed. A first interlevel dielectric film 55 is formed over the Si substrate 51. Memory cell capacitors are formed at respective regions over the LOCOS film 52 on the first interlevel dielectric film 55. Each of these memory cell capacitors includes: a bottom electrode 56 made of a metal such as platinum or iridium; a ferroelectric film 57 made of a ferroelectric material; and a top electrode 58 also made of a metal such as platinum or iridium. A second interlevel dielectric film 59 is formed over the first interlevel dielectric film 55. And storage lines 60, made of aluminum containing copper, are formed on the second interlevel dielectric film 59.
In FIG. 4, the gates 54 and bottom electrodes 56 extend along the rows of the array as word lines WL0, WL1, WL2 and WL3 and cell plate lines CP0, CP1, CP2 and CP3, respectively. A group of bit lines BL0, /BL0, BL1, /BL1, DBL and /DBL are formed to extend along the columns of the array. One of these bit lines, i.e., a bit line DBL, is illustrated in FIG. 5 by a phantom line. Each top electrode 58 shown in FIG. 5 corresponds to a data storage node of a DRAM, and is identified by TE in FIG. 4. Each storage line 60 is connected to an associated top electrode 58 via a contact CE and to an associated doped layer 53 of the memory cell transistor via a contact CW1. Each bit line BL0, /BL0, BL1, /BL1, DBL or /DBL is connected to an associated doped layer 53 via a contact CW2. And the respective storage lines 60 and the group of bit lines BL0, /BL0, BL1, /BL1, DBL and /DBL constitute a first interconnection layer.
In this device, data can be retained as either “0” or “1” by holding a ferroelectric film 57 in either positively or negatively polarized state depending on a level difference between a voltage on a bit line supplied via an associated doped layer 53 and a voltage on an associated cell plate line.
The reliability of this ferroelectric memory device sometimes deteriorates due to the infant mortality failure of the ferroelectric capacitor or degradation in retention characteristics thereof. The present inventors carried out intensive research to find out measures to be taken for solving this problem. As a result of experiments, we obtained data suggesting that the decrease in reliability might have been brought about probably because a storage line 60 exists over an excessively wide range above an associated top electrode 58 of a ferroelectric capacitor.